CMPE224 Digital Logic Systems

CMPE224 Outline

Department: Computer Engineering

 Instructor Information
Name: Assoc. Prof. Dr. Muhammed Salamah

 E-mail: muhammed.salamah@emu.edu.tr

Office: CMPE 114

Office Tel: 1149


Program Name:  Computer Engineering                                                            Program Code: 25

Course Number:CMPE224                                        Credits: 4 Cr                       Year/Semester:2023-2024 Spring

Required Course           Elective Course       (click on and check the appropriate box)



CMPE223 Digital Logic Design

Catalog Description

This course presents the basic tools for the design of synchronous sequential circuits and covers methods and procedures suitable for a variety of digital design applications in computers, control systems, data communications, etc.. Concentration will be on widely-used design methods for synchronous sequential circuits together with their analysis and simulation in VHDL.

Course Web Page:    https://staff.emu.edu.tr/muhammedsalamah/en/teaching/cmpe224


S. Brown and Z. Vranesic, "Fundamentals of Digital Logic with VHDL Design", McGraw-Hill, Third Edition, 2009.

Indicative Basic Reading List :

Richard S. Sandige. "Digital Design Essentials," Prentice-Hall 2002.

John F. Wakerly, "Digital Design: Principles and Practices" Pearson Education, 2006.

Topics Covered and Class Schedule:

(4 hours of lectures per week)

Week 1
Synchronous sequential logic(SSL), flip-flops (FFs), VHDL implementation of FFs.

Week 2 
Analysis of clocked sequential circuits, state transition tables/diagrams.

Week 3
Design of clocked sequential circuits, design procedure, state reduction and assignment, flip-flop excitation tables.

Week 4
Design procedure & case studies.

Week 5
Design of counters.

Week 6
VHDL implementation of SSL

Week 7
Registers & shift registers

Week 8
Asynchronous ripple counters

Week 9
Synchronous counters & timing sequences

Week 10
VHDL implementation of registers and counters.

Week 11

Characteristics of ASM flow chart, timing considerations

Week 12
Data-path implementation

Week 13
Control-path implementation

Week 14
Further issues in VHDL implementation of synchronous sequential circuits

Week 15
Design case studies.

Laboratory Schedule:

(2 hours of laboratory per week)

Week 4            Introduction to Quartus 8 Development Environment.

Week 5            VHDL implementation of FFs.

Week 6            Behavioral VHDL implementation of SSL.

Week 7            Structural implementation of SSL.

Week 8            VHDL implementation of registers and counters.

Week 9            VHDL implementation state-machines.

Week 10         Structural VHDL implementation of Datapath and Controlpath.

Week 11         VHDL dataflow architectures.

Course Learning Outcomes:

Upon successful completion of the course, students are expected to have the following competencies:

(1)     Design sequential logic circuits using state diagrams, state tables, and Flip-Flop excitation tables (b1,b2,b3)

(2)     Ability to analyze sequential logic circuits by constructing the state tables / state diagrams and find their functions (e1,e2,e3)

(3)     Ability to derive truth tables, characteristic equations, and excitation tables of Flip-Flops (a1,a2,a3)

(4)     Ability to draw timing diagrams for sequential logic circuits (a2,a3)

(5)     Ability to construct initial state transition diagrams, perform state reduction and assignment from the verbal description of the circuit behavior (e1,e2,e3)

(6)     Design synchronous and asynchronous (ripple) counters using intuitive approaches (b1,b3)

(7)     Ability to design and analyze various types of registers (b1,b2,b3)

(8)     Construct and/or trace ASM charts for digital hardware algorithms (e1,e2,e3)

(9)     Design and construct digital control and datapath circuits using ASM charts (b1,b2)

(10)   Ability to use CAD tools (Quartus) to simulate and verify sequential logic circuits (k1,k2,k3)

  Method No Percentage 
AssessmentMidterm Exam(s)125 % 
Quizzes220 % 
 Labs~715 % 
 Final Examination140 % 

Policy on makeup: There is no makeup for the quizzes. Only one makeup exam can be given for one of the missed exams (midterm or final) according to the University regulations. In order to be able to enter a makeup exam, you MUST submit a written report to your instructor stating your excuse within 3 days of that examination.

Policy on NG grades: 

NG grade will be given in the following cases: Lab attendance < 50% or Missing both Midterm and Final Exams.

Contribution of Course to Criterion 5

Credit Hours for:

Mathematics & Basic Science : 0

Engineering Sciences and Design : 4

General Education : 0

Relationship of Course to Program Outcomes

The course has been designed to contribute to the following program outcomes:

a)  an ability to apply knowledge of mathematics, science, and engineering.

b)  an ability to design and conduct experiments, as well as to analyze and interpret data

e)  an ability to identify, formulate, and solve engineering problems.

k)  an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice

Prepared by: Assoc.Prof.Dr. Muhammed Salamah

Date Prepared: Feb. 27, 2017